1. Field of the Invention
The present invention relates to electronic design automation (EDA), and to modeling delay changes arising for example from implementation of changes in cells of an integrated circuit design for performance optimization.
2. Description of Related Art
One approach to EDA supported design is based on the definition of an integrated circuit using a computer system as a netlist of circuit elements. Also, a cell library is provided that specifies characteristics of cells available for use in a physical implementation using a given technology of the circuit elements in the netlist. The entries in the library include layout data, performance data such as delay models and power models, and other supporting information. To implement the netlist, cells are selected from the library, placed in a layout space, and interconnections are defined among the cells. The selection of cells, placement of cells and defining interconnections among the cells can be referred to as placement and routing. The result of a place and route procedure is a layout file which specifies the shapes and locations of components of the cells, and the interconnections of the cells which are to be made into an integrated circuit.
The cell library has a finite number of choices for the circuit elements. Adding cells to the library is costly, as each cell in the library is prequalified for manufacturability and other factors.
Small layout changes, such as transistor gate length increases, can be used to optimize integrated circuits for performance, such as to reduce leakage power, etc. (See, Lawrence T. Clark et al., “Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design,” ISLPED 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design, Aug. 9-11, 2004.
Transistors with above-nominal gate lengths have been proposed and used in VLSI designs to reduce the active mode leakage power (i.e., runtime leakage). See, Puneet Gupta et al. “Selective gate-length biasing for cost-effective runtime leakage control,” Proceedings of the 41st Design Automation Conference, 2004 (Gupta 1); Shekhar Borkar et al., “Parameter variations and impact on circuits and microarchitecture” Proceeding of the Design Automation Conference, 2-6 Jun. 2003; Qian Ying Tang, et al. “Phenomenological model for gate length bias dependent inverter delay change with emphasis on library characterization,” ISQED 2009, Quality of Electronic Design, 16-18 Mar. 2009; and Puneet Gupta et al., “Gate-length biasing for runtime-leakage control,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, Issue 8, August 2006 (Gupta 2).
Gate length biasing can be implemented either on the cell level or on the transistor level. See, Tang; Gupta 2; Saumil Shah, et al., “Standard cell library optimization for leakage reduction,” Design Automation Conference, 2006 43rd ACM/IEEE; and Lawrence T. Clark et al., “Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design,” ISLPED 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design, Aug. 9-11, 2004. The resulting lower-performance, lower-leakage standard cell variants are then exploited to replace as many cell instances as possible on design paths with positive timing slack (Gupta 2).
The values of the gate length bias are usually chosen to ensure footprint equivalence and complete interchangeability between cell masters (i.e. the initial form of the cell in the library entry) and cell variants (i.e., modified cells), and the number of allowable biases may vary. For example, the dual-gate-length (DGL) approach allows the nominal gate length and one bias only. The multi-gate-length (MGL) technique, however, can use many bias values with fine increments on the cell level. MGL, similar to the within-cell transistor-level biasing, results in finer levels of granularity in delay-leakage trade-off on the cell level. Intuitively, finer levels of granularity could translate into better leakage reduction on the design level, in part by moving timing paths closer to the guard-banded zero slack timing point. Previous studies, however, reported inconsistent findings, with some showing noticeable additional leakage reduction and others observing very little advantage by using finer levels of granularity.
So gate length changes and other small changes that affect cell performance such as voltage thresholds and leakage power can be made to optimize performance of a design after placement and routing using a standard cell library.
Procedures applied to optimize circuit designs using these techniques typically involve constrained optimization procedures, where the adjustments made are constrained by their effect on delay as constrained by available slack. Such procedures depend on the ability to compute the delay changes with reasonable computing resources, so that they can be accomplished without undue cost.
In practice, what is often more important during design optimization or physical implementation is to capture the variations in delay as a function of changes in cell/device parameters such as the gate length. While previous works have primarily focused on modeling the delay itself, they are relatively ineffective in capturing the changes in delay. Also, modeling for the purposes of library characterization can be prohibitively expensive using prior models because of the explosively huge number of cell variants that might be needed in a robust library to optimization processes.
It is desirable therefore to provide design automation tools for modeling delay changes due to modifications of cells to enable designers to apply constrained optimization procedures to implement such modifications.